Abstract: A kind of scalable array architecture based on DA implementation is proposed.Better scalability and high parallel processing efficiency can be obtained by array configuration.Compared with traditional ASIC implementation，this architecture not only properly solves the problems of disability of self adaptation of order and data word width，but also solves the problem of large storage requirement and low throughput of ASIC.The implementation cost and performance comparison with typical architecture are presented in the last part，which demonstrate that the proposed architecture has lower memory requirements，lower time cost and better performance-cost ratio.

Key words: distributed arithmetic, Parallel DA（PDA）, PE array, prefix-accumulation

摘要： 提出一种基于DA实现的可扩展的阵列结构，通过对阵列的配置使其具有良好的扩展能力以及并行处理的高效特性。该结构与传统的采用ASIC电路的实现方式相比，较好地解决了ASIC电路中阶数、数据字宽不可自适应调整以及存储量需求较大、吞吐量偏低的问题。最后在实现代价和性能方面与典型结构进行了比较，证明了该结构存储量需求小，运算时间少，具有较好的性价比。

关键词: 分布算术, 并行DA, PE阵列, 前缀求和