[1] |
YUAN Fuli, GONG Lei, LOU Wenqi, CHEN Xianglan.
Performance Cost Modeling in Dynamic Reconfiguration Hardware Acceleration
[J]. Computer Engineering and Applications, 2022, 58(6): 69-79.
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[2] |
GUO Zibo, GAO Yingke, HU Hangtian, GONG Duo, LIU Kai, WU Xianyun.
Research on Acceleration of Convolutional Neural Network Algorithm Based on Hybrid Architecture
[J]. Computer Engineering and Applications, 2022, 58(6): 88-94.
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[3] |
GUO Jun, YU Zhiguo, HONG Guangwei, GU Xiaofeng.
Design of Firmware Update System Based on RISC-V Processor
[J]. Computer Engineering and Applications, 2022, 58(4): 298-303.
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[4] |
WANG Tengfei, ZHANG Haifeng, XU Sen.
Design and Implementation of SM2 Co-processor with Specific Instructions
[J]. Computer Engineering and Applications, 2022, 58(2): 102-109.
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[5] |
ZHANG Wei, ZHOU Hua, LIU Yuhong, ZHANG Rongfen.
Research on Optic Disc and Macula Fovea Simultaneous Location and Detection Method on FPGA
[J]. Computer Engineering and Applications, 2022, 58(11): 193-199.
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[6] |
YAN Fei, MA Ke, LIU Jia, LIU Yinping, XIA Jinfeng.
UAV Target Real-Time Adaptive Tracking System
[J]. Computer Engineering and Applications, 2022, 58(10): 178-184.
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[7] |
DU Yuzhang, PAN Jiahua, ZONG Rong, SU Wei, WANG Weilian.
Lightweight Network Heart Sound Classifier Based on Hardware Acceleration
[J]. Computer Engineering and Applications, 2021, 57(23): 263-269.
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[8] |
JIANG Peihe, WANG Chenxu, GUO Gang, WEI Yinsheng.
Research on Hardware Trojan Detection for FPGA Application
[J]. Computer Engineering and Applications, 2021, 57(20): 119-124.
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[9] |
LENG Ming, SUN Lingyu, GUO Chen.
Forward Circuit Generation Algorithm of XDL Netlist
[J]. Computer Engineering and Applications, 2021, 57(10): 75-80.
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[10] |
WU Yiyang, FAN Fan, ZHOU Yi, HUANG Jun.
FPGA Implementation of Affine Transformation Based on Pre-interpolation
[J]. Computer Engineering and Applications, 2020, 56(6): 224-230.
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[11] |
WANG Meile, ZHANG Zhizhong, XI Bing.
Feasibility Analysis of Downlink Baseband Board for LTE-A Air Interface Analyzer
[J]. Computer Engineering and Applications, 2020, 56(4): 268-273.
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[12] |
ZHANG Wei, LIU Yuhong, ZHANG Rongfen.
Design of IP Cores for CNN Convolutional Layer and Pooling Layer Capable of Time Division Multiplexing
[J]. Computer Engineering and Applications, 2020, 56(24): 66-71.
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[13] |
WU Jin, ZHANG Weihua, XI Meng, DAI Wei.
Optimized Design and FPGA Implementation of High-Performance Face Recognition Accelerator
[J]. Computer Engineering and Applications, 2020, 56(22): 48-54.
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[14] |
WANG Fan, ZHOU Guoqing, ZHANG Rongting, LIU Dequan.
FPGA-Oriented Fast Connected Component Labeling Method
[J]. Computer Engineering and Applications, 2020, 56(22): 230-235.
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[15] |
ZHANG Xinwei, LI Kang, YU Gongjian, LIU Jiahang, LI Peiqi, CHAI Zhilei.
Research and Implementation of Accelerating Neuromorphic Computing Based on ZYNQ Cluster
[J]. Computer Engineering and Applications, 2020, 56(21): 65-71.
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