Abstract: The adoption of multiple macroblock partitions with variable block sizes is one of the main reasons behind the high efficiency of H.264 video coding standard. Unfortunately, Repeating Sum of Absolute Difference(SAD) calculations for every possible block size introduces a heavy computational cost, in order to reduce the Encdoer complexity, this paper proposes an hardware architecher for integrate full block match algorithm(FBMA), with reusing a common set of SAD computations for motion estimation of small blocks and a 2D shifting search window，the processing speed is greatly promoted. Simulation shows that it can get 41 MVs and the responeding SAD within only 324 circles, and the processing speed is nearly six times as fast as the other hardware solutions

Key words: H.264/AVC, motion estimation, variable block-size

摘要： H.264视频编码的高效率体现在多种分块模式的运动估计，然而，反复的针对各种分块模式的绝对和的计算会给编码器带来极大的负担。为减小编码器的复杂度，本文提出了一种适合硬件实现的整像素全搜索硬件结构体系，通过重用各种子块的SAD值，以及2维移位搜索窗的引入，大大提高了运算速度，仿真结果表明，本文提出的硬件结构体系可以在324个周期内完成一个宏块41个运动矢量的计算及相应的SAD值，与其他方案相比速度提高了近6倍。

关键词: H.264/AVC, 运动估计, 可变块尺寸