Computer Engineering and Applications ›› 2006, Vol. 42 ›› Issue (27): 16-.

• 博士论坛 • Previous Articles    

Design of a Novel FFT Processor for DVB-T System

JiaChong Zhou,   

  1. 同济大学通信软件及ASIC研发中心
  • Received:2006-07-10 Revised:1900-01-01 Online:2006-09-21 Published:2006-09-21
  • Contact: JiaChong Zhou

一种适用于DVB-T系统的新型FFT处理器设计

周加铳,陈咏恩   

  1. 同济大学通信软件及ASIC研发中心
  • 通讯作者: 周加铳 norad

Abstract: A novel mixed radix-16/8 FFT algorithm and architecture were presented suitable for terrestrial digital video broadcasting (DVB-T) system. By using a single radix-16/8 butterfly processing element and reducing the number of multipliers, the proposed approach obtained significant hardware reduction. To achieve high speed processing, the “radix-4 + radix-4/2” cascade pipeline architecture was designed in radix-16/8 butterfly unit. Furthermore, a symmetry ping-pang RAM structure was adopted to increase the continuous computing capability of the butterfly core. Computing precision was also enhanced through a modified block floating point anti-overflow scheme. Simulation and hardware implementation results show that the proposed method performs well and can meet the needs of the given application.

Key words: symmetry ping-pang RAM structure, anti-overflow, fast Fourier transform, butterfly processing element, pipeline

摘要: 针对地面数字视频广播(DVB-T)系统中高速FFT处理器的设计要求,提出了一种新的基16/8混合基算法及其实现结构。采用单个基16/8复用的蝶形运算单元顺序处理,并通过减少乘法器数目,有效降低硬件消耗;运算单元内部采用“基4+基4/2”级联流水线方式,大大加快运算速度;此外,应用对称乒乓RAM结构提高了蝶算单元的连续运算能力;并且使用改进的块浮点防溢出机制,以保证运算精度。仿真和实现结果表明本设计具有良好的性能,完全满足实际应用要求。

关键词: 对称乒乓RAM结构, 防溢出, 快速傅立叶变换, 蝶形运算单元, 流水线