Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (8): 64-66.DOI: 10.3778/j.issn.1002-8331.2010.08.018

• 研发、设计、测试 • Previous Articles     Next Articles

High speed FFT butterfly unit and addresses generator optimization

WANG Zhen-dao,WANG Yu-feng,CHEN Di-ping   

  1. College of Physics and Microelectronics Science,Hunan University,Changsha 410082,China
  • Received:2009-06-03 Revised:2009-08-05 Online:2010-03-11 Published:2010-03-11
  • Contact: WANG Zhen-dao



  1. 湖南大学 物理与微电子科学学院,长沙 410082
  • 通讯作者: 王镇道

Abstract: An optimized method of butterfly unit and addresses generator is proposed.By improving the Wallace tree adder array structure,the frequency of butterfly unit multiplier is improved.The rapid algorithm of addresses generation is proposed,with this algorithm,the addresses can be generated quickly,and the power of reading twiddles ROM is decreased.With Vertex-II series FPGA of Xilinx,the design is implemented,the system can operate stably at 150 MHz,the speed meets the requirements.

摘要: 提出了FFT处理器的蝶形单元和地址发生器优化方案。通过改进Wallace树型加法器阵列结构,提高了蝶形单元乘法器的工作频率。提出了地址快速生成算法,该算法在快速产生地址的同时降低了读取旋转因子ROM的功耗。在Xilinx的Vertex-II系列FPGA上实现,该处理器可以稳定工作在150 MHz时钟下,速度满足设计指标。

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